Phase Change Memory Cell With First and Second Transition Temperature Portions

ABSTRACT

A phase change memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. The phase change bridge may extend over the generally coplanar surfaces and across the gap. The phase change bridge has a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. A method for making a phase change memory cell is also disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent application Ser. No. 11/424,177, filed on 14 Jun. 2006, which application claims the benefit of U.S. Provisional Patent Application No. 60/740,176 entitled “Phase Change Memory Cell and Manufacturing Method” filed on 28 Nov. 2005, both of which are incorporated by reference for all purposes.

PARTIES TO A JOINT RESEARCH AGREEMENT

International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies AG, a German corporation, are parties to a Joint Research Agreement.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, and referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meets tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure that meets tight process variation specifications needed for large-scale memory devices.

SUMMARY OF THE INVENTION

A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits.

A first aspect of the invention is directed to a phase change memory cell, the memory cell being a part of a phase change memory device. The memory cell includes first and second electrodes having generally coplanar surfaces spaced apart by a gap and a phase change bridge electrically coupling the first and second electrodes. At least a section of the phase change bridge comprises a higher transition temperature bridge portion and a lower transition temperature portion. The lower transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher transition temperature portion. In some embodiments the section of the phase change bridge comprises first and second of the higher transition temperature portion located on different sides of the lower transition temperature portion. The phase change bridge may extend over the generally coplanar surfaces on the first and second electrodes and across the gap.

A second aspect of the invention districts to a method for making a phase change memory cell, the memory cell being a part of a phase change memory device, comprising electrically coupling first and second generally coplanar surfaces of first and second electrodes with a phase change bridge, the phase change bridge comprising phase change material. The electrically coupling step comprises providing a higher transition temperature portion and a lower transition temperature portion, the lower transition temperature portion creating a phase change region which can be transitioned between generally crystalline and generally amorphous states by the passage of electrical current between the electrodes. In some embodiments the providing step comprises changing the transition temperature of the phase change material of at least a section of the phase change bridge to create the higher transition temperature portion and the lower transition temperature portion by implanting a part of the section of the phase change bridge with a material to increase the transition temperature of said part thereby creating the higher transition temperature portion.

The method described herein for formation of the bridge for use in a memory cell in the PCRAM, can be used to make a very small bridge for other uses. Nano-technology devices with very small bridge structures are provided using materials other than phase change to materials, like metals, dielectrics, organic materials, semiconductors, and so on.

Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a thin film bridge phase change memory element.

FIG. 2 illustrates a current path in a thin film bridge phase change memory element as shown in FIG. 1.

FIG. 3 illustrates an active region for phase changes in a thin film bridge phase change memory element as shown in FIG. 1.

FIG. 4 illustrates dimensions for a thin film bridge phase change memory element as shown in FIG. 1.

FIG. 5 illustrates a structure for a pair of phase change memory elements with access circuitry below an electrode layer and bit lines above the electrode layer.

FIG. 6 shows a layout or plan view for the structure illustrated in FIG. 5.

FIG. 7 is a schematic diagram for a memory array comprising phase change memory elements.

FIG. 8 is a block diagram of an integrated circuit device including a thin film fuse phase change memory array and other circuitry.

FIG. 9 is a cross-section of a substrate that includes access circuitry formed by front-end-of-line processes, made in a process for manufacturing a phase change memory device based on the structure shown in FIG. 5.

FIG. 10 is a cross-section showing initial steps in formation of an electrode layer for the structure shown in FIG. 5.

FIGS. 11A and 11B show layout and cross-sectional views for patterning the structure of FIG. 10, forming electrode stacks in the electrode layer for the structure shown in FIG. 5.

FIG. 12 shows a cross-sectional view corresponding to steps for formation of sidewall insulators on the electrode stacks of FIG. 11B.

FIG. 13 shows a cross-sectional view corresponding to steps for formation of a layer of conductor material over the structure of FIG. 12.

FIG. 14 shows a cross-sectional view corresponding to steps for polishing the conductive material and sidewall insulators in the structure of FIG. 13.

FIG. 15 shows a cross-sectional view corresponding to steps for forming a thin film layer of phase change material and a protective cap layer on the structure of FIG. 14.

FIGS. 16A and 16B show layout and cross-sectional views for patterning the thin film layer of phase change material of FIG. 15, forming strips of photoresist on the phase change material.

FIGS. 17A and 17B show layout and cross-sectional views for patterning the thin film layer of phase change material of FIG. 15, after etching the strips of photoresist of FIGS. 16A and 16B to form narrow strips of photoresist.

FIGS. 18A and 18B show layout and cross-sectional views of the strips of phase change material after etching the thin film layer of phase change material according to the pattern of photoresist shown in FIGS. 17A and 17B.

FIGS. 19A and 19B show layout and cross-sectional views for patterning the strips of phase change material of FIGS. 18A and 18B, used to form bridges of phase change material on the electrode layer.

FIGS. 20A and 20B show layout and cross-sectional views of the bridges of phase change material after etching according to the pattern of FIGS. 19A and 19B.

FIG. 21 shows a cross-sectional view corresponding to steps for forming a dielectric fill layer over the structure shown in FIGS. 20A and 20B, including the electrode layer and the bridges of phase change material.

FIGS. 22A and 22B show layout and cross-sectional views after formation of conductive plugs in the dielectric fill layer contacting the bridges of phase change material in the structure shown in FIG. 21.

FIG. 23 shows a cross-sectional view corresponding to steps for forming a patterned conductive layer structure over the structure shown in FIGS. 22A and 22B.

FIG. 24 illustrates a phase change material deposited on top of first and second electrodes, the electrode separated by an insulation member.

FIG. 25 shows the structure of FIG. 24 after photoresist mask deposition and etching steps.

FIG. 26 shows the structure of FIG. 25 after a mask trimming step.

FIG. 27 illustrates implantation of an element into the exposed portions of the phase change material.

FIGS. 28 and 29 are overall and cross-sectional views of the phase change memory cell after removal of the photoresist mask.

FIG. 30 illustrates an alternative to the implantation technique of FIG. 27 in which implantation is at an angle so to create a smaller phase change region.

FIG. 31 is a cross-sectional view taken along line 31-31 of FIG. 30 illustrating the narrowed phase change region created by the angled implantation.

DETAILED DESCRIPTION

A detailed description of thin film fuse phase change memory cells, arrays of such memory cells, and methods for manufacturing such memory cells, is provided with reference to FIGS. 1-23. The embodiments of FIGS. 24-31 are examples of phase change memory cells having higher and lower transition temperature portions.

The following description of the invention will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Like elements in various embodiments are commonly referred to with like reference numerals.

FIG. 1 illustrates a basic structure of a memory cell 10 including a bridge 11 of memory material on an electrode layer which comprises a first electrode 12, a second electrode 13, and an insulating member 14 between the first electrode 12 and the second electrode 13. As illustrated, the first and second electrodes 12, 13 have top surfaces 12 a and 13 a. Likewise the insulating member 14 has a top surface 14 a. The top surfaces 12 a, 13 a, 14 a of the structures in the electrode layer define a substantially planar top surface for the electrode layer in the illustrated embodiment. The bridge 11 of memory material lies on the planar top surface of the electrode layer, so that contacts between the first electrode and the bridge 11 and between the second electrode 13 and the bridge 11 are made on the bottom side of the bridge 11.

FIG. 2 shows a current path 15 between the first electrode 12, the bridge 11, and the second electrode 13 formed by the memory cell structure. Access circuitry can be implemented to contact the first electrode 12 and the second electrode 13 in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the bridge 11 in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state.

FIG. 3 shows the active channel 16 in the bridge 11, where the active channel 16 is the region in which the material is induced to change between the at least two solid phases. As can be appreciated, the active channel 16 can be made extremely small in the illustrated structure, reducing the magnitude of current needed to induce the phase changes.

FIG. 4 illustrates important dimensions of the memory cell 10. The length L α-dimension) of the active channel is defined by the thickness of the insulating member 14 (called channel dielectric in the figure), between the first electrode 12 and the second electrode 13. This length L can be controlled by controlling the width of the insulating member 14 in embodiments of the memory cell. In representative embodiments, the width of the insulating member 14 can be established using a thin film deposition technique to form a thin sidewall dielectric on the side of an electrode stack. Thus, embodiments of the memory cell have a channel length L less than 100 nm. Other embodiments have a channel length L of about 40 nm or less. In yet other embodiments, the channel length is less than 20 nm. It will be understood that the channel length L can be even smaller than 20 nm, using thin film deposition techniques such as atomic layer deposition and the like, according to the needs of the particular application.

Likewise, the bridge thickness T (y-dimension) can be very small in embodiments of the memory cell. This bridge thickness T can be established using a thin film deposition technique on the top surfaces of the first electrode 12, insulating member 14, and second electrode 13. Thus, embodiments of the memory cell have a bridge thickness T about 50 nm or less. Other embodiments of the memory cell have a bridge thickness of about 20 nm or less. In yet other embodiments, the bridge thickness T is about 10 nm or less. It will be understood that the bridge thickness T can be even smaller than 10 nm, using thin film deposition techniques such as atomic layer deposition and the like, according to the needs of the particular application, so long as the thickness is sufficient for the bridge performs its purpose as memory element, having at least two solid phases, reversible by a current or by a voltage applied across the first and second electrodes.

As illustrated in FIG. 4, the bridge width W (z-dimension) is likewise very small. This bridge width W is implemented in preferred embodiments, so that it has a width less than 100 nm. In some embodiments, the bridge width W is about 40 nm or less.

Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the bridge 11. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te_(a)Ge_(b)Sb_(100−(a+b)).

One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge₂Sb₂Te₅, GeSb₂Te₄ and GeSb₄Te₇. (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.

Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ge₂Sb₂Te₅ commonly referred to as GST.

The invention has been described with reference to phase change materials. However, other memory materials, also sometimes referred to as programmable materials, can also be used. As used in this application, memory materials are those materials having electrical properties, such as resistance, that can be changed by the application of energy; the change can be a stepwise change or a continuous change or a combination thereof. Other programmable resistive memory materials may be used in other embodiments of the invention, including N2 doped GST, GexSby, or other material that uses different crystal phase changes to determine resistance; PrxCayMnO3, PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; TCNQ, PCBM, TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse. Further examples of programmable resistive memory materials include GeSbTe, GeSb, NiO, Nb—SrTiO3, Ag—GeTe, PrCaMnO, ZnO, Nb2O5, Cr—SrTiO3.

For additional information on the manufacture, component materials, use and operation of phase change random access memory devices, see U.S. patent application Ser. No. 11/155,067, filed 17 Jun. 2005, entitled Thin Film Fuse Phase Change Ram And Manufacturing Method, Attorney Docket No. MXIC 1621-1.

FIG. 5 depicts a structure for PCRAM cells. The cells are formed on a semiconductor substrate 20. Isolation structures such as shallow trench isolation STI dielectrics (not shown) isolate pairs of rows of memory cell access transistors. The access transistors are formed by n-type terminal 26 acting as a common source region and n-type terminals 25 and 27 acting as drain regions in a p-type substrate 20. Polysilicon word lines 23 and 24 form the gates of the access transistors. A dielectric fill layer (not illustrated) is formed over the polysilicon word lines. The layer is patterned and conductive structures, including common source line 28 and plug structures 29 and 30 are formed. The conductive material can be tungsten or other materials and combinations suitable for the plug and lines structures. The common source line 28 contacts the source region 26, and acts as a common source line along a row in the array. The plug structures 29 and 30 contact the drain terminals 25 and 26, respectively. The fill layer (not shown), the common source line 28 and the plug structures 29 and 30, have a generally planar top surface, suitable for formation of an electrode layer 31.

The electrode layer 31 includes electrode members 32, 33 and 34, which are separated from one another by an insulating member including fences 35 a and 35 b formed for example by a sidewall process as described below, and base member 39. The base member 39 can be thicker than the fences 35 a, 35 b in embodiments of the structure, and separates the electrode member 33 from the common source line 28. For example the base member can be for instance, 80 to 140 nm thick while the fences are much narrower, as needed to reduce capacitive coupling between the source line 28 and the electrode member 33. The fences 35 a, 35 b comprise a thin film dielectric material on the sidewalls of electrode members 32, 34 in the illustrated embodiment, with a thickness at the surface of the electrode layer 31 determined by the thin film thickness on the sidewalls.

A thin film bridge 36 of memory material, such as GST, overlies the electrode layer 31 on one side traversing across the fence member 35 a, forming a first memory cell, and a thin film bridge 37 of memory material, such as GST, overlies the electrode layer 31 on another side traversing across the fence member 35 b, forming a second memory cell.

A dielectric fill layer (not illustrated) overlies the thin film bridges 36, 37. The dielectric fill layer comprises silicon dioxide, a polyimide, silicon nitride or other dielectric fill materials. In embodiments, the fill layer comprises a relatively good insulator for heat as well as for electricity, providing thermal and electrical isolation for the bridges. Tungsten plug 38 contacts the electrode member 33. A patterned conductive layer 40, comprising metal or other conductive material, including bit lines in an array structure, overlies the dielectric fill layer, and contacts the plug 38 to establish access to the memory cells corresponding to the thin film bridge 36 and the thin film bridge 37.

FIG. 6 shows the structure above the semiconductor substrate layer 20 of FIG. 5 in layout view. Thus, the word lines 23 and 24 are laid out substantially parallel to the common source line 28, along those in an array of memory cells. Plugs 29 and 30 contact terminals of access transistors in the semiconductor substrate and the underside of electrode members 32 and 34 respectively. Thin film bridges 36 and 37 of memory material overlie the electrode members 32, 33 and 34, and the insulating fences 35 a, 35 b separating the electrode members. Plug 38 contacts the electrode member 33 between the bridges 36 and 37 and the underside of a metal bit line 41 (transparent in FIG. 6) in the patterned conductive layer 40. Metal bit line 42 (not transparent) is also illustrated in FIG. 6 to emphasize the array layout of the structure.

In operation, access to the memory cell corresponding with bridge 36 is accomplished by applying a control signal to the word line 23, which couples the common source line 28 via terminal 25, plug 29, and electrode member 32 to the thin-film bridge 36. Electrode member 33 is coupled via the contact plug 38 to a bit line in the patterned conductive layer 40. Likewise, access to the memory cell corresponding with bridge 37 is accomplished by applying a control signal to the word line 24.

It will be understood that a wide variety of materials can be utilized in implementation of the structure illustrated in FIGS. 5 and 6. For example, copper metallization can be used. Other types of metallization, including aluminum, titanium nitride, and tungsten based materials can be utilized as well. Also, non-metal conductive material such as doped polysilicon can be used. The electrode material in the illustrated embodiment is preferably TiN or TaN. Alternatively, the electrodes may be TiAlN or TaAlN, or may comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. The inter-electrode fence members 35 a, 35 b may be silicon oxide, silicon oxynitride, silicon nitride, Al2O3, or other low K dielectrics. Alternatively, the inter-electrode insulating layer may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C.

FIG. 7 is a schematic illustration of a memory array, which can be implemented as described with reference to FIGS. 5 and 6. Thus, reference numerals for elements of FIG. 7 match corresponding elements in the structure of FIGS. 5 and 6. It will be understood that the array structure illustrated in FIG. 7 can be implemented using other cell structures. In a schematic illustration of FIG. 7, the common source line 28, the word line 23 and the word line 24 are arranged generally parallel in the Y-direction. Bit lines 41 and 42 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block 45 are coupled to the word lines 23, 24. An X-decoder and set of sense amplifiers in block 46 are coupled to the bit lines 41 and 42. The common source line 28 is coupled to the source terminals of access transistors 50, 51, 52 and 53. The gate of access transistor 50 is coupled to the word line 23. The gate of access transistor 51 is coupled to the word line 24. The gate of access transistor 52 is coupled to the word line 23. The gate of access transistor 53 is coupled to the word line 24. The drain of access transistor 50 is coupled to the electrode member 32 for bridge 36, which is in turn coupled to electrode member 34. Likewise, the drain of access transistor 51 is coupled to the electrode member 33 for bridge 36, which is in turn coupled to the electrode member 34. The electrode member 34 is coupled to the bit line 41. For schematic purposes, the electrode member 34 is illustrated at separate locations on the bit line 41. It will be appreciated that separate electrode members can be utilized for the separate memory cell bridges in other embodiments. Access transistors 52 and 53 are coupled to corresponding memory cells as well on line 42. It can be seen that the common source line 28 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. Likewise, the electrode member 34 is shared by two memory cells in a column in the array, where a column is arranged in the X-direction in the illustrated schematic.

FIG. 8 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 74 includes a memory array 60 implemented using thin film fuse phase change memory cells, on a semiconductor substrate. A row decoder 61 is coupled to a plurality of word lines 62, and arranged along rows in the memory array 60. A column decoder 63 is coupled to a plurality of bit lines 64 arranged along columns in the memory array 60 for reading and programming data from the multiple-gate memory cells in the array 60. Addresses are supplied on bus 65 to column decoder 63 and row decoder 61. Sense amplifiers and data-in structures in block 66 are coupled to the column decoder 63 via data bus 67. Data is supplied via the data-in line 71 from input/output ports on the integrated circuit 75 or from other data sources internal or external to the integrated circuit 75, to the data-in structures in block 66. In the illustrated embodiment, other circuitry is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film fuse phase change memory cell array. Data is supplied via the data-out line 72 from the sense amplifiers in block 66 to input/output ports on the integrated circuit 75, or to other data destinations internal or external to the integrated circuit 75.

A controller implemented in this example using bias arrangement state machine 69 controls the application of bias arrangement supply voltages 68, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.

FIG. 9 illustrates a structure 99 after front-end-of-line processing, forming the standard CMOS components in the illustrated embodiment corresponding to the word lines, the source line, and the access transistors in the array shown in FIG. 7. In FIG. 9, source line 106 overlies doped region 103 in the semiconductor substrate, where the doped region 103 corresponds with the source terminal of a first access transistor on the left in the figure, and of a second access transistor on the right in the figure. In this embodiment, the source line 106 extends to the top surface of the structure 99. In other embodiments the source line does not extend all the way to the surface. Doped region 104 corresponds with the drain terminal of the first access transistor. A word line including polysilicon 107, and silicide cap 108, acts as the gate of the first access transistor. Dielectric layer 109 overlies the polysilicon 107 and silicide cap 108. Plug 110 contacts doped region 104, and provides a conductive path to the surface of the structure 99 for contact to a memory cell electrode as described below. The drain terminal of the second access transistor is provided by doped region 105. A word line including polysilicon line 111, and the silicide cap (not labeled) acts as the gate for the second access transistor. Plug 112 contacts doped region 105 and provides a conductive path to the top surface of the structure 99 for contact to a memory cell electrode as described below. Isolation trenches 101 and 102 separate the two-transistor structure coupled to the plugs 110 and 112, from adjacent two-transistor structures. On the left, word line polysilicon 117 and plug 114 are shown. On the right, word line polysilicon 118 and plug 113 are shown. The structure 99 illustrated in FIG. 9 provides a substrate for formation of memory cell components, including the first and second electrodes, and the bridge of memory material, as described in more detail below.

FIG. 10 illustrates a next stage in the process, in which a thin dielectric layer 120 comprising silicon nitride SiN or other material, is formed on the surface of the structure 99. Then a layer 121 of conductive electrode material such as titanium nitride TiN is formed on the dielectric layer 120.

FIGS. 11A and 11B illustrate a next stage in the process, in which the conductive electrode layer 121 and the dielectric layer 120 are patterned to define electrode stacks 130, 131 and 132 on the surface of the structure 99. In an embodiment, the electrode stacks are defined by a mask lithographic step that produces a patterned layer of photoresist, followed by dimension measurement and verification steps known in the art, and then etching of the TiN and SiN used for formation of the layers 121 and 120. The stacks have sidewalls 133 and 134.

FIG. 12 illustrates a next stage in the process, in which dielectric sidewalls 140, 141, 142 and 143 are formed on the sidewalls of the stacks 130, 131, 132, by forming a thin film dielectric layer (not shown) that is conformal with the stacks and the sidewalls of the stacks, and then anisotropically etching the thin film dielectric to remove it from the regions between the stacks and on the surfaces of the stacks, while remaining on the sidewalls. In embodiments of the process, the material used for formation of the sidewalls 140, 141, 142 and 143 comprises SiN or other dielectric material, such as silicon dioxide, silicon oxynitride, aluminum oxide, and the like.

FIG. 13 illustrates a next stage in the process, in which a second electrode material layer 150 is formed over the stacks 130, 131 132 and the sidewalls 140, 141, 142, 143. The electrode material layer 150 comprises TiN or other suitable conductive material, such as TaN, aluminum alloys, copper alloys, doped polysilicon, etc.

FIG. 14 illustrates a next stage in the process, in which the second electrode material layer 150, the sidewalls 140, 141, 142, 143 and the stacks 130, 131, 132 are etched and planarized to define an electrode layer over the substrate provided by structure 99. Embodiments of the process for polishing include a chemical mechanical polishing process, followed by brush clean and liquid and or gas clean procedures, as known in the art. The electrode layer includes electrode members 160, 161, 162, and insulating members 163 and 164 in between them. The electrode layer in the illustrated embodiment has a substantially planar top surface. In the embodiment shown, the insulating members 163 and 164 comprise portions of a structure which also extends beneath electrode member 161, isolating it from the source line. Other example structures may use different materials for the electrode members and insulating members.

FIG. 15 illustrates a next stage in the process, in which a thin film layer 170 of a phase change based memory material is formed on the substantially planar top surface of the electrode layer. The memory material is deposited using sputtering without collimation at about 250 degrees C. This results in a thin film having a thickness of about 60 nanometers or less, when using Ge2Sb2Te5 as the phase change memory material. Embodiments involve sputtering the entire wafer to thickness of about 40 nanometers on the flat surfaces. The thin film layer 170 has a thickness less than 100 nm in some embodiments, and more preferably 40 nm or less. In embodiments of the memory device, the thin film layer 170 has a thickness of less than 20 nm, such as 10 nm. After forming the thin film layer 170, a protective cap layer 171 is formed. The protective cap layer 171 comprises a low-temperature deposited silicon dioxide or other dielectric material formed over the thin film layer 170. The protective cap layer 171 is preferably a good electrical insulator and a good thermal insulator, and protects the memory material from exposure in subsequent steps, such photoresist stripping steps which can damage the material. The process involves formation of a low-temperature liner dielectric, such as a silicon nitride layer or silicon oxide layer, using a process temperature less than about 200 degrees C. One suitable process is to apply silicon dioxide using PECVD. After formation of the protective cap layer 171, a dielectric fill over the memory material can be implemented using a higher temperature process such as high-density plasma HDP CVD.

FIGS. 16A and 16B illustrate a next stage in the process, in which a photoresist layer 180 is formed and patterned in a mask lithographic process to define strips 180 a, 180 b over the thin film layer 170 and protective cap layer 171. As seen in FIG. 16A, the insulating members 163 and 164 are exposed between the strips 180 a, 180 b of photoresist. The strips of photoresist are made as narrow as possible according to the lithographic process applied. For example, the strips have a width equal to the minimum feature size F for the lithographic process used, where the minimum feature size for a process may be on the order of 0.2 microns (200 nm), 0.14 microns, or 0.09 microns in current mask lithographic processes. Obviously, embodiments of the process can be adapted to narrower minimum feature sizes as lithographic processes advance.

FIGS. 17A and 17B illustrate a next stage in the process, in which the photoresist strips 180 a, 180 b of FIG. 16A are trimmed to form more narrow photoresist strips 190 a, 190 b. As shown in FIG. 17B, the trimmed photoresist 190 is also thinner than the photoresist layer 180 of FIG. 16B. In one embodiment, the photoresist strips are trimmed by isotropic etching using a reactive ion etch process or otherwise. The etching trims the photoresist strips to more narrow line widths. Embodiments of the more narrow photoresist strips 190 a, 190 b are less than 100 nm wide. In other embodiments the more narrow photoresist strips 190 a, 190 b are about 40 nm or less wide. Photoresist trimming is applied using an oxide plasma to isotropically etch the photoresist, which trims its width and thickness down to a width of for example about 40 nanometers in a 0.09 micron (90 nanometer) minimum feature size lithographic process environment. In an alternative, a hard mask layer, such as a low temperature deposited layer of SiN or SiO2 can be put on the bottom of the photoresist pattern to prevent etching damage of the memory material during the photoresist stripping process.

FIGS. 18A and 18B illustrate a next stage in the process, in which the more narrow photoresist strips 190 a, 190 b are used for an etch mask, and the thin film layer 200 of memory material is etched to lithographically define strips 200 a, 200 b of memory material, with or without the protective cap layer 201. As shown, the strips 200 a, 200 b span across the insulating members 163, 164, and the electrode members in the electrode layer. In embodiments of the process the memory material comprises a GST chalcogenide based material, and is etched using for example, a chlorine-based or fluorine-based, reactive ion etching process.

FIGS. 19A and 19B illustrate a next stage in the process, in which another photoresist layer 210, 211 is formed and patterned to define photoresist structures 210 a, 210 b, 211 a, 211 b, 212 a and 212 b. The cell structures correspond with pairs of memory cells as described below. The cell structures are wider than the strips 200 a, 200 b of memory material because they have a width equal to the width achieved using the lithographic process applied in the manufacturing process, such as a photomask based lithographic process, without trimming. Thus, the width in some embodiments is equal to the minimum feature size F for the lithographic process applied in forming the layer.

FIGS. 20A and 20B illustrate a next stage in the process, in which the photoresist structures 210 a, 210 b, 211 a, 211 b, 212 a and 212 b are used as etch masks to define cell structures 220 a, 220 b, 221 a, 221 b, 222 a and 222 b by etching trenches 225, 226 to the isolation dielectric structures in the structure 99, and the trenches 227 between columns of cells orthogonal to the word lines. The cell structure 220 a includes a first electrode member 215, a second electrode member 216 and a third electrode member 217. Insulating member 163 separates the first electrode member 215 from the second electrode member 216. Insulating member 164 separates the first electrode member 215 from the third electrode member 217. A bridge 218 of memory material overlies the electrode members 215, 216 and 217 and the insulating members 163, 164 to establish two memory cells on the structure 220.

FIG. 21 illustrates a next stage in the process, in which a dielectric fill layer 230 with a planar top surface is formed over the electrode structures and fills the gaps and trenches between them. In an embodiment of the process, the fill layer 230 is formed by high-density plasma HDP chemical vapor deposition CVD, followed by chemical mechanical polishing and cleaning. The dielectric fill may comprise silicon oxides, silicon nitrides, and other insulating materials, preferably having good thermal as well as electrical insulating properties.

In some embodiments a structure for thermally insulating the bridges is provided, in addition to or instead of the dielectric fill layer. In one example, the thermally insulating structure is formed by providing a cap layer of thermally insulating material over the bridges (218) and optionally over the electrode layer, before applying the dielectric fill. Representative materials for the layer of thermally insulating material include materials that are a combination of the elements silicon Si, carbon C, oxygen O, fluorine F, and hydrogen H. Examples of thermally insulating materials which are candidates for use for the thermally insulating cap layer include SiO2, SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for the thermally insulating cap layer include fluorinated SiO2, silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. In other embodiments, the thermally insulating structure comprises a gas-filled void in the dielectric fill formed over the bridge 218 for thermal insulation. A single layer or combination of layers can provide thermal and electrical insulation.

FIGS. 22A and 22B illustrate a next stage in the process, in which vias (not shown) are etched in the fill layer 230 to the electrode material, through the memory material and the fill. The via etch process may be a single anisotropic etch for both the fill and the memory material, or a two step process first etching the fill material with a first etch chemistry, and second etching the memory material with a second etch chemistry. After forming the vias, the vias are filled with tungsten or other conductive material, to form plugs 240, 241 and 242 contacting the first electrode member (e.g. member 215) in the electrode structures, for electrical communication with circuitry above the electrode layer. In embodiments of the process, the vias are lined with a diffusion barrier layer and/or an adhesion layer, as known in the art, and filled with tungsten or other suitable conductive material. The structure is then planarized by chemical mechanical polishing and cleaned. Finally a “clean up” etch is applied and the resulting structure is cleaned.

FIG. 23 illustrates a next stage in the process, in which a patterned conductive layer 250 is formed in contact with the plugs over the fill layer, providing bit lines and other conductors for the memory device, yielding the structure shown and described above with respect to FIG. 5. In embodiments of the process, a copper alloy damascene metallization process is used in which the patterned conductive layer is formed depositing fluorosilicate glass (FSG) on the exposed surface, and then forming a photoresist pattern in the pattern desired. An etch is applied removing exposed FSG, and then liner and seed layers are deposited in the pattern. Then, copper plating is applied to fill the pattern. After plating, an anneal step is applied, followed by a polishing process. Other embodiments can use standard Al-Cu processes, or other metallization processes known in the art.

A cell described herein comprises two bottom electrodes with a dielectric spacer in between and a bridge of phase change material on the top of the electrodes spanning across the spacer. The bottom electrodes and dielectric spacer are formed in an electrode layer over front-end-of-line CMOS logic structures or other function circuit structures, providing a structure that easily support embedded memory and function circuits on a single chip, such as chips referred to as system on a chip SOC devices.

FIGS. 24-31 illustrate a further embodiment of a phase change memory cell made according to the invention. FIG. 24 illustrates first and second electrodes 312, 313 separated by an insulation member 314. A phase change material 316 is deposited over electrodes 312, 313 and insulation member 314. FIG. 25 illustrates results of depositing a photoresist mask 318 over phase change material 316 followed by the removal of phase change material 316 not covered by mask 318, typically through an appropriate etching procedure. This creates a phase change element, specifically a phase change bridge 311 of phase change material. Thereafter photoresist mask 318 is trimmed to create the reduced size mask 320 of FIG. 26. The width of reduced size mask 320 is well below the minimum photolithographic feature size used to create mask 318. Trimming is typically by a photoresist oxygen plasma trimming process but may be by other processes as well. Reduced size mask 320 is positioned generally centrally along the length of phase change bridge 311 to expose bridge 311 to implantation as suggested in FIG. 27.

Implantation 322, such as ion implantation, may be accomplished with an element, or combination of elements, that increases the transition temperature of phase change material 316 both when phase change material 316 transitions from generally amorphous to generally crystalline states and especially during reset, that is when phase change material 316 transitions from generally crystalline to generally amorphous states. Examples of such elements include carbon, silicon, nitrogen, and aluminum. Removal of mask 318 results in phase change memory cell 310, including phase change bridge 311, of FIGS. 28 and 29. Phase change bridge 311 includes higher transition temperature portions 324 on either side of lower transition temperature portion 326. In this preferred embodiment implantation is used to raise the transition temperature of portions of phase change bridge 311. In one embodiment the transition temperature of higher transition temperature portions 324 is typically at least about 100° C. greater than the transition temperature of lower transition temperature portion 326 when the higher transition temperature portion 324 is in a generally amorphous state and of the lower transition temperature portion 326 is in a generally crystalline state. As electricity passes between first and second electrodes 312, 313, a phase change region 328 of portion 326, located above insulation member 314, can transition between generally crystalline and generally amorphous states before the implanted phase change material of portions 324 on either side of region 328 can make such transition. In some embodiments implantation may be used to lower the transition temperature of portion 326 instead of or in addition to raising the transition temperature of portions 324.

FIGS. 30 and 31 illustrate higher angle implantation 330 which creates a narrowed phase change region 328 compared to phase change region 328 of FIG. 29. This helps to further concentrate current at phase change region 328 to help reduce the current and power required to create the desired generally crystalline to generally amorphous phase change.

An advantage of the invention discussed above with regard to FIGS. 24-31 is that by isolating phase change region 328 of lower transition temperature portion 326 between higher transition temperature portions 324, greater thermal isolation of phase change region 328 is achieved thereby reducing reset current and power.

Another aspect of the invention relates to the thermal conductivity of the higher and lower transition temperature portions 324, 326 when both are in the same generally crystalline or generally amorphous state. Preferably, the thermal conductivity of higher transition temperature portions 324 is less than, and more preferably at least about 50% less than, the thermal conductivity of lower transition temperature portion 326 when both are in generally amorphous states. Similarly, the thermal conductivity of higher transition temperature portions 324 is less than, and more preferably at least about 50% less than, the thermal conductivity of lower transition temperature portion 326 when both are in generally amorphous states. These factors help to further thermally isolate phase change region 328 of portion 326. Examples of appropriate implant elements include nitrogen, oxygen and silicon.

A further aspect of the invention relates to the electrical resistivity of the higher and lower transition temperature portions 324, 326. Preferably the electrical resistivity of higher transition temperature portion 324 is greater than, and more preferably at least about 50% greater than, the electrical resistivity of lower transition temperature portion 326 when both are in generally amorphous states. Similarly, the electrical resistivity of higher transition temperature portion 324 is greater than, and more preferably at least about 50% greater than, the electrical resistivity of lower transition temperature portion 326 when both are in generally crystalline states. In addition, the electrical resistance of higher transition temperature portion 324 is preferably greater than, and more preferably at least about 50% greater than, the electrical resistance of lower transition temperature portion 326 when both are in generally amorphous states. Similarly, the electrical resistance of higher transition temperature portion 324 is preferably greater than, and more preferably at least about 50% greater than, the electrical resistance of lower transition temperature portion 326 when both are in generally crystalline states. These aspects help to concentrate electrical current through phase change region 328 of lower transition temperature portion 326 to help reduce transition current and power, especially during reset.

It is preferred that higher transition temperature portion 324 be in and remain in its generally amorphous state because the thermal and electrical conductivity of materials in a generally amorphous state are typically less than the thermal and electrical conductivity in a generally crystalline state.

The above descriptions may have used terms such as above, below, top, bottom, over, under, et cetera. These terms are used to aid understanding of the invention are not used in a limiting sense.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.

Any and all patents, patent applications and printed publications referred to above are incorporated by reference. 

1. A phase change memory cell, comprising: first and second electrodes; a phase change memory element electrically coupling the first and second electrodes; and at least a section of the phase change memory element comprising a first transition temperature portion and a second transition temperature portion, wherein the transition temperature of the first transition temperature portion is higher than the transition temperature of the second transition temperature portion.
 2. The phase change memory cell according to claim 1, wherein the first and second electrodes have generally coplanar surfaces spaced apart by a gap.
 3. The phase change memory cell according to claim 1, wherein the second transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the first transition temperature portion.
 4. The phase change memory cell according to claim 1, wherein the transition temperature of the first transition temperature portion is at least about 100° C. greater than the transition temperature of the second transition temperature portion.
 5. The phase change memory cell according to claim 1, wherein the thermal conductivity of the first transition temperature portion is less than the thermal conductivity of the second transition temperature portion when both are in generally crystalline states.
 6. The phase change memory cell according to claim 1, wherein the thermal conductivity of the first transition temperature portion is at least about 50% less than the thermal conductivity of the second transition temperature portion when both are in generally crystalline states.
 7. The phase change memory cell according to claim 1, wherein the electrical resistivity of the first transition temperature portion is greater than the electrical resistivity of the second transition temperature portion when both are in generally crystalline states.
 8. The phase change memory cell according to claim 1, wherein the electrical resistivity of the first transition temperature portion is at least about 50% greater than the electrical resistivity of the second transition temperature portion when both are in generally crystalline states.
 9. The phase change memory cell according to claim 1, wherein the electrical resistance of the first transition temperature portion is greater than the electrical resistance of the second transition temperature portion when both are in generally crystalline states.
 10. The phase change memory cell according to claim 1, wherein the electrical resistance of the first transition temperature portion is at least about 50% greater than the electrical resistance of the second transition temperature portion when both are in generally crystalline states.
 11. The phase change memory cell according to claim 1, wherein the section of the phase change memory element comprises third and fourth of the first transition temperature portion located on different sides of the second transition temperature portion.
 12. The phase change memory cell according to claim 1, wherein the first transition temperature portion has an element implanted therein, said element being effectively absent from the second transition temperature portion.
 13. The phase change memory cell according to claim 12, wherein said element comprises at least one of carbon, silicon, oxygen, nitrogen and aluminum.
 14. The phase change memory cell according to claim 1, wherein the phase change memory element comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
 15. The phase change memory cell according to claim 1, wherein the first and second electrodes comprise an element selected from a group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. 